About SmartDV Technologies
Company Description
SmartDV Technologies is a leading provider of verification IP (VIP) and testing solutions for semiconductor and electronic design automation (EDA). With a commitment to innovation and quality, SmartDV empowers its clients to achieve faster and more reliable product development in the rapidly evolving technology landscape. The company fosters a culture of collaboration, creativity, and continuous learning, where employees are encouraged to share ideas and think outside the box. The work environment at SmartDV is dynamic and inclusive, promoting a healthy work-life balance while emphasizing professional growth. Employees are supported through training programs, mentorship opportunities, and a focus on teamwork, making it an excellent place for both seasoned professionals and newcomers to the field.
Software Engineer Interview Questions
Q1: What programming languages are you most proficient in?
I am most proficient in C++, SystemVerilog, and Python. I have used these languages extensively in my previous projects related to verification and design automation.
Q2: Can you describe a challenging project you worked on and how you overcame the difficulties?
In one of my previous projects, I faced a challenge with a complex verification environment that had numerous dependencies. I overcame this by breaking down the environment into manageable modules, using a systematic approach for integration and testing, which significantly improved our efficiency.
Q3: How do you ensure the quality of your code?
I ensure the quality of my code by following best practices such as writing modular code, conducting thorough unit tests, and participating in code reviews with my peers. I also utilize static code analysis tools to catch potential issues early.
Q4: What is your experience with verification methodologies like UVM?
I have a solid understanding and hands-on experience with UVM (Universal Verification Methodology). I have implemented several testbenches using UVM, which helped streamline the verification process and improve code reuse.
Q5: How do you stay updated with the latest trends in technology and software development?
I stay updated by reading industry-related articles, participating in online courses, and attending workshops and conferences. I am also part of several online communities where I engage with other professionals and share knowledge.
Verification Engineer Interview Questions
Q1: What is your experience with verification IP?
I have worked extensively with various verification IPs, including those for PCIe, USB, and Ethernet protocols. This experience has helped me develop a deep understanding of their functionalities and usage in different projects.
Q2: Describe a time when you had to debug a complex issue in a verification environment.
I encountered a complex issue where the simulation results did not match the expected outcomes. By systematically analyzing the logs and using waveform analysis tools, I identified that a timing issue in the clock domain crossing was the root cause, which I resolved by adjusting the synchronization mechanisms.
Q3: How do you approach test planning and writing test cases?
I start by understanding the specifications and requirements thoroughly. Then, I create a test plan outlining the scenarios to be covered. For writing test cases, I focus on both positive and negative scenarios, ensuring that edge cases are also included to validate the robustness of the design.
Q4: What tools do you commonly use for verification?
I commonly use tools like ModelSim, VCS, and Questa for simulation. For formal verification, I have experience with JasperGold and other formal tools to ensure comprehensive coverage.
Q5: How do you handle tight deadlines while maintaining quality in your work?
I prioritize tasks based on their importance and impact, breaking down larger tasks into smaller, manageable parts. I also communicate regularly with my team to ensure alignment and address any obstacles promptly, allowing us to meet deadlines without compromising on quality.
Design Engineer Interview Questions
Q1: What design methodologies are you familiar with?
I am familiar with various design methodologies, including RTL design, behavioral modeling, and system-level design. I have experience using tools like Cadence Genus and Synopsys Design Compiler for synthesis.
Q2: Can you describe a successful design project you completed?
In a recent project, I led the design of a low-power ASIC. I implemented techniques like clock gating and power gating, which resulted in a significant reduction in power consumption while maintaining performance metrics.
Q3: How do you ensure that your designs meet timing and performance requirements?
I ensure that my designs meet timing and performance requirements by performing thorough timing analysis using static timing analysis tools. I also utilize iterative design and verification processes to refine and optimize the design throughout the development cycle.
Q4: What experience do you have with FPGA development?
I have experience developing designs for FPGAs using VHDL and Verilog. I have worked on projects that required rapid prototyping, allowing for quick iterations and testing of design concepts.
Q5: How do you approach collaboration with verification engineers?
I believe that early collaboration with verification engineers is crucial. I involve them in the design phase to discuss potential verification challenges and create a clear interface and specifications that facilitate smooth verification processes.
Project Manager Interview Questions
Q1: What project management methodologies are you familiar with?
I am familiar with Agile, Scrum, and Waterfall methodologies. I have successfully managed projects using Scrum, focusing on iterative development, regular feedback, and adaptability to changes.
Q2: How do you handle project scope changes?
I handle scope changes by first assessing the impact on the project timeline and resources. I then communicate with stakeholders to discuss the changes, evaluate priorities, and adjust the project plan accordingly while ensuring transparency.
Q3: Can you describe a challenging project you managed and how you ensured its success?
I managed a project with a tight deadline and limited resources. To ensure success, I prioritized tasks, delegated responsibilities effectively, and maintained constant communication with the team. We conducted daily stand-ups to address any issues promptly, ultimately delivering the project on time.
Q4: How do you measure project success?
I measure project success by evaluating whether the project meets its objectives, stays within budget, and is delivered on time. I also consider stakeholder satisfaction and the quality of the final deliverables.
Q5: How do you motivate your team during challenging phases of a project?
I motivate my team by fostering a positive work environment, recognizing individual contributions, and providing support and resources they need. Encouraging open communication and celebrating small wins helps maintain morale during challenging phases.
Company Background and Industry Position
SmartDV Technologies is a prominent player in the semiconductor IP domain, specializing in verification IP, embedded IP, and design automation tools. Founded with a vision to streamline complex chip design and verification processes, the company has carved out a niche by delivering highly efficient, ready-to-use IP cores and verification methodologies. Their clientele spans major semiconductor companies globally, which positions SmartDV as a trusted partner in an industry where precision and speed are everything.
In the competitive landscape of semiconductor IP providers, SmartDV stands out due to its robust focus on innovation and customer-centric solutions. The company’s emphasis on quality and turnkey offerings has enabled it to maintain relevance despite rapid technological shifts. Within the broader context of chip design and verification, SmartDV’s solutions help reduce time-to-market—a crucial advantage in a fiercely competitive marketplace.
How the Hiring Process Works
- Application and Resume Screening – The initial step involves a detailed filtering of candidates based on their resumes and relevant qualifications. Recruiters focus on educational background, technical skills, and prior experience related to semiconductor IP or verification domains.
- Technical Assessment – This can be an online test or a take-home assignment. The goal is to evaluate core competencies such as RTL design, SystemVerilog, UVM, or other relevant verification methodologies. Candidates usually face logic design problems and coding challenges.
- Technical Interview – A deep dive into candidate knowledge with senior engineers or architects. This round tests problem-solving skills, understanding of verification environments, and domain expertise.
- HR Interview – Here, the focus shifts to cultural fit, communication skills, career aspirations, and salary expectations. It’s also when discussion around company policies, benefits, and role responsibilities happens.
- Final Decision and Offer – Based on collective feedback, successful candidates receive an offer with details on compensation, joining timeline, and role specifics.
The process is designed not just to assess technical acumen but to evaluate adaptability to fast-paced R&D teams. SmartDV places a premium on hiring individuals who can think beyond textbook solutions, given the complex nature of semiconductor verification work.
Interview Stages Explained
Technical Screening and Assessment
This stage is less about rote knowledge and more about practical problem-solving. Candidates often encounter questions that simulate real challenges in verification script writing or debugging existing IP designs. The rationale here is clear: SmartDV wants to ensure that applicants can hit the ground running.
Interestingly, this phase often separates candidates who are theoretically strong from those who truly understand the verification ecosystem. It’s not unusual for candidates to be asked to write code snippets or explain their approach to system-level verification strategies.
In-Depth Technical Interview
Once past initial screening, candidates face a more narrative and interactive interview. Senior engineers pose scenario-based questions that require not only an answer but also justification. For example, candidates might be asked how they would optimize a UVM testbench or troubleshoot coverage holes.
This round sheds light on a candidate’s analytical mindset and familiarity with industry-standard tools like Questa, VCS, or Cadence platforms. Candidates who engage actively, ask clarifying questions, and demonstrate curiosity tend to fare better.
HR Interview and Soft Skills Evaluation
The human side of hiring. It’s where recruiters assess if the applicant’s personality and work style align with SmartDV’s collaborative environment. Questions about conflict resolution, teamwork, and long-term career goals are common.
Salary negotiations and benefits discussions happen here too, but with a transparent and respectful tone. Candidates appreciate when the HR team is upfront about expectations, reducing guesswork.
Examples of Questions Candidates Report
- Technical Questions: “Explain how UVM sequences work and how you would customize them for a new verification component?”
- Problem Solving: “Given an RTL module with a timing violation, describe your approach to identifying the root cause.”
- Coding Challenge: “Write a SystemVerilog function to implement a random stimulus generator with coverage points.”
- Behavioral: “Tell us about a time when you had to handle a disagreement within your project team. How did you manage it?”
- Scenario-Based: “How would you improve the efficiency of a regression test suite that’s currently taking too long to execute?”
These questions highlight the company’s focus on both technical depth and interpersonal effectiveness. Candidates often note the technical rounds require fresh thinking rather than textbook recitations.
Eligibility Expectations
SmartDV Technologies looks for candidates primarily with strong academic credentials in electronics, computer engineering, or related fields. Typically, a bachelor’s degree is the minimal requirement, with many roles preferring a master’s or equivalent experience, especially in verification domains.
Prior experience with semiconductor design verification, knowledge of verification languages like SystemVerilog, UVM methodology, and practical exposure to industry tools are essential. For fresh graduates, internships or project experience demonstrating understanding of verification concepts can be a deciding factor.
Soft skills such as communication, problem-solving, and adaptability are also non-negotiable. Given the company’s collaborative culture, candidates must demonstrate eagerness to learn and work in teams.
Common Job Roles and Departments
SmartDV’s hiring broadly revolves around several key departments:
- Verification IP Development: Engineers who develop reusable verification IP blocks aligned with industry standards.
- Design Verification: Roles focusing on verifying RTL designs using UVM and other methodologies.
- Embedded IP Development: Engineers working on embedded memory controllers, interfaces, and other IPs.
- Software Development: Teams building automation tools and custom verification environments.
- Sales and Marketing: Professionals who translate technical details into customer value propositions.
Each role demands specific expertise, but all share a reliance on strong domain knowledge and ability to keep pace with evolving semiconductor trends.
Compensation and Salary Perspective
| Role | Estimated Salary (INR/year) |
|---|---|
| Verification Engineer (Entry-Level) | 6,00,000 - 9,00,000 |
| Senior Verification Engineer | 12,00,000 - 20,00,000 |
| Embedded IP Engineer | 8,00,000 - 15,00,000 |
| Software Developer (Verification Tools) | 7,00,000 - 14,00,000 |
| HR & Recruitment Specialist | 4,50,000 - 8,00,000 |
Compared to other semiconductor IP firms, SmartDV offers competitive packages, often supplemented by performance bonuses and stock options, especially for senior roles. The salary range reflects the technical complexity and criticality of the positions within the company.
Interview Difficulty Analysis
Candidates typically find the SmartDV interview process moderately challenging. The technical rounds require solid understanding, but not to the extent of some giant MNCs on sheer volume. The key difficulty lies in the application of concepts rather than memorization.
Many applicants mention feeling the pressure during scenario-based questions since these do not have a “right” answer but test thought process and communication clarity. The HR round is generally straightforward, though candidates should be prepared to discuss their career path candidly.
In essence, if you are comfortable with verification methodologies and can articulate your reasoning clearly, the difficulty curve should be manageable. Candidates inexperienced in UVM or SystemVerilog may find it harder, underscoring the importance of preparation.
Preparation Strategy That Works
- Understand verification methodologies deeply—focus on SystemVerilog and UVM as they are staples in interviews.
- Practice debugging RTL and writing small verification environments. Real coding experience trumps theoretical knowledge.
- Review common interview questions reported by previous candidates and frame your answers with examples from past work or projects.
- Simulate scenario-based questions with peers or mentors to improve your problem-solving articulation.
- Keep updated on industry trends, tools, and SmartDV’s product offerings to show genuine interest.
- Prepare clear, concise narratives for behavioral questions—reflect on past challenges and teamwork experiences.
- During the HR round, be honest about salary expectations but back your ask with market research.
- Don’t underestimate the power of asking insightful questions to your interviewers; it shows engagement.
Work Environment and Culture Insights
SmartDV promotes a culture of innovation balanced with pragmatism. The work environment is often described as collaborative yet demanding, with a strong emphasis on continual learning and quality delivery.
The company encourages engineers to take ownership of their modules and fosters open communication across teams. Many employees appreciate the relatively flat hierarchy, which allows for direct interaction with senior technical leaders.
However, given the nature of product delivery in semiconductor IP, timelines can be tight, and adaptability is essential. The culture rewards those who demonstrate initiative and resilience.
Career Growth and Learning Opportunities
SmartDV invests in skill development regularly, offering internal technical sessions, access to industry conferences, and mentorship programs. The company’s focus on cutting-edge verification technology means employees are constantly exposed to new methodologies.
Career trajectories often lead from individual contributor roles to technical leadership or product management. Given the niche expertise developed here, individuals find ample opportunities to advance both vertically and horizontally within the semiconductor industry.
Long-term employees often cite the opportunity to work with global clients and challenging projects as a key factor in their professional growth.
Real Candidate Experience Patterns
From conversations with past applicants, a few themes emerge. Most candidates find the initial screening tough but fair. Many mention that the technical interview is interactive, with interviewers keen to see how one thinks under pressure rather than just perfect answers.
Some applicants feel the HR round is less formal than expected, often concluding with a friendly discussion where candidates get honest insights into the company’s expectations. A handful have noted that preparation for scenario-based questions made a huge difference in their confidence.
On the flip side, some freshers have struggled when lacking hands-on verification exposure, which underlines the company’s preference for practical skills over pure academics.
Comparison With Other Employers
When benchmarked against other semiconductor IP firms and verification service providers, SmartDV offers a balanced mix of innovation-driven roles with moderately rigorous recruitment. Unlike larger MNCs where the process can be highly bureaucratic, SmartDV's hiring rounds feel more personalized and technical.
In terms of compensation, the company competes well with mid-tier firms but might offer slightly less than giant players like Synopsys or Cadence on senior positions. However, the work environment is often praised for being less hierarchical and more flexible, which appeals to a particular demographic.
| Aspect | SmartDV Technologies | Major Competitors |
|---|---|---|
| Interview Complexity | Moderate, emphasis on practical skills | High, extensive multi-stage |
| Salary Range | Competitive mid-tier | Often higher for senior roles |
| Work Culture | Collaborative, innovative | Varies, often more formal |
| Career Development | Strong focus on verification tech | Broader opportunities |
Expert Advice for Applicants
If you’re aiming for a role at SmartDV, focus on mastering verification fundamentals and getting hands-on practice with UVM and SystemVerilog. Don’t just memorize concepts—understand why certain methodologies exist and how they solve real problems.
During interviews, be curious. Ask questions about the product, team dynamics, or challenges the company faces. This shows genuine engagement rather than robotic rehearsed responses.
Also, prepare stories that highlight your problem-solving skills and teamwork. SmartDV values candidates who can navigate ambiguity and collaborate effectively in fast-evolving projects.
Lastly, manage expectations. The hiring process isn’t about perfect answers but demonstrating a growth mindset and technical versatility.
Frequently Asked Questions
What are the main technical skills SmartDV looks for in candidates?
Strong knowledge of SystemVerilog, UVM, RTL design, and verification methodologies is crucial. Practical experience with semiconductor verification tools and scripting enhances your chances significantly.
How many interview rounds should I expect?
Typically, there are three to four stages: initial screening (online test or resume shortlisting), technical interview(s), and HR interview.
Is prior experience mandatory?
Not necessarily for entry-level roles, but some hands-on project or internship experience in verification is highly preferred, especially for technical positions.
What is the typical salary range for fresh graduates?
Entry-level verification engineers can expect between INR 6,00,000 to 9,00,000 per annum, depending on location and skill set.
How should I prepare for scenario-based interview questions?
Practice explaining your reasoning clearly. Use examples from past experiences or projects. Understand the verification process deeply so you can propose practical solutions rather than generic answers.
Final Perspective
SmartDV Technologies offers an exciting gateway into the specialized world of semiconductor IP verification. Its hiring process strikes a thoughtful balance between technical rigor and cultural fit, demanding candidates to bring both depth and adaptability. While the journey can be demanding, those who embrace the preparation strategy centered around practical skill-building and clear communication often find themselves rewarded with meaningful roles and growth opportunities.
For job seekers passionate about chip design verification, SmartDV stands out as a company where you can immerse yourself in cutting-edge challenges while growing steadily within a close-knit, innovative community. Approach the interview with confidence, a learning mindset, and readiness to solve real-world problems, and you’ll navigate their recruitment landscape much smoother than most expect.
SmartDV Technologies Interview Questions and Answers
Updated 21 Feb 2026Sales Engineer Interview Experience
Candidate: Vikram Singh
Experience Level: Mid-level
Applied Via: Recruitment agency
Difficulty:
Final Result: Rejected
Interview Process
3 rounds
Questions Asked
- How do you approach technical sales?
- Explain a successful sales experience.
- Describe your knowledge of semiconductor industry.
- Behavioral: How do you handle rejection?
Advice
Gain deeper technical understanding of the products and prepare to demonstrate sales strategies with examples.
Full Experience
The interview process involved a mix of technical and sales-oriented questions. While the team appreciated my communication skills, they wanted stronger technical expertise.
Technical Support Engineer Interview Experience
Candidate: Priya Menon
Experience Level: Mid-level
Applied Via: LinkedIn
Difficulty:
Final Result:
Interview Process
3 rounds
Questions Asked
- How do you troubleshoot hardware issues?
- Explain a time you resolved a complex technical problem.
- What tools do you use for debugging?
- Behavioral: How do you prioritize support tickets?
Advice
Demonstrate strong problem-solving skills and clear communication. Be prepared with examples of past support challenges.
Full Experience
The first round was a technical phone interview, followed by a practical test on troubleshooting. The final round was with HR and team lead focusing on behavioral aspects.
Field Application Engineer Interview Experience
Candidate: Suresh Kumar
Experience Level: Senior
Applied Via: Company website
Difficulty: Easy
Final Result:
Interview Process
2 rounds
Questions Asked
- Explain how you handle customer technical issues.
- Describe your experience with semiconductor products.
- Behavioral: Describe a time you managed a difficult client.
Advice
Focus on communication skills and technical knowledge relevant to the product line. Be ready to share real-world customer interaction experiences.
Full Experience
The interview was mostly conversational with emphasis on past experience and problem-solving skills in customer-facing roles. The HR round was brief and positive.
Software Engineer Interview Experience
Candidate: Anita Desai
Experience Level: Entry-level
Applied Via: Employee referral
Difficulty: Hard
Final Result: Rejected
Interview Process
4 rounds
Questions Asked
- Data structures and algorithms problems.
- Explain your project experience.
- Write code to reverse a linked list.
- What is your understanding of embedded systems?
- Behavioral: How do you handle tight deadlines?
Advice
Prepare thoroughly on coding problems and understand embedded software basics. Practice mock interviews to improve confidence.
Full Experience
The interview process was intense with multiple coding rounds and technical questions. The HR round was straightforward but technical rounds were challenging for an entry-level candidate.
Verification Engineer Interview Experience
Candidate: Rahul Sharma
Experience Level: Mid-level
Applied Via: Online job portal
Difficulty:
Final Result:
Interview Process
3 rounds
Questions Asked
- Explain UVM methodology.
- How do you write assertions in SystemVerilog?
- Describe your experience with simulation tools.
- Behavioral: Describe a challenging bug you found and fixed.
Advice
Brush up on SystemVerilog and UVM concepts, and be ready to discuss past verification projects in detail.
Full Experience
The first round was a technical phone screen focusing on basics of verification and SystemVerilog. The second round was a detailed technical interview with coding and debugging exercises. The final round was with the team lead and HR, focusing on culture fit and behavioral questions.
Frequently Asked Questions in SmartDV Technologies
Have a question about the hiring process, company policies, or work environment? Ask the community or browse existing questions here.
Common Interview Questions in SmartDV Technologies
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Q: In a Park, N persons stand on the circumference of a circle at distinct points. Each possible pair of persons, not standing next to each other, sings a two-minute song ? one pair immediately after the other. If the total time taken for singing is 28 minutes, what is N?
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